1. Field of the Invention
This invention relates broadly in the field of binary digital logical circuitry and in particular is concerned with an envelope generator for an electronic musical instrument.
2. Description of the Prior Art
It is well known that the ordinary complement of a number represented digitally as a binary number is obtained by forming a new binary sequence of digits in which for any bit position j, the new values are 1-n.sub.j where n.sub.j is the corresponding value of the original binary number for the same bit position j. If the original binary number is represented by N binary digits, then the decimal numerical value corresponding to the complement is (2.sup.N -1) minus the decimal value of the original binary number before forming the complement.
In the usage of binary number terminology, the ordinary complement is sometimes simply called the "complement." The ordinary complement is also called the 1's complement to differentiate it from the operation known as the 2's complement. For binary digital numbers, the 2's complement is obtained by first forming the complement and then adding a "1" to the least significant bit while permitting a carry bit as required in turn to all the more significant bit positions in sequence.
The implementation of a 1's complementor circuitry for an ordinary, or fixed point, binary number consists of a simple state inversion operator which is easily implemented with digital logic gate invertors.
By analogy with the common representation of a decimal number as a floating point number, the same decimal number can also be represented in the form of a floating point binary number. The binary floating point number representation of a decimal number having the value A is defined by an expression of the form EQU A=(1+a.sub.1 2.sup.-1 +a.sub.2 2.sup.-2 a.sub.3 2.sup.-3 + . . . +a.sub.k 2.sup.-k).times.2.sup.J, (Eq. 1)
where the coefficients a.sub.j have either a value of 0 or 1.
The conventional method of forming the 1's complement for a number A represented as a binary floating point number in the form shown in Eq. 1 consists of implementing the following three operation steps:
(1) convert the given binary floating point number to its equivalent fixed point binary number,
(2) construct the 1's complement of the equivalent fixed point binary number,
(3) convert the resulting 1's complemented number to a binary floating point number.
Each of the preceding steps can readily be implemented using known state of the art digital logic circuits. One disadvantage to using the conventional method of forming the complement of a binary floating number lies in the required comparatively large number of digital logic gates used to implement the three operation steps.
The present invention provides a novel means for implementing digital circuitry for directly performing the complement of a binary floating point number without performing the preceding three steps of the conventional method.
An example of the application of the present invention is to the envelope function generator for an electronic musical instrument as described in U.S. Pat. No. 4,144,789 entitled "Amplitude Generator For An Electronic Organ." The envelope function generator described in the referenced patent creates an exponentially decreasing set of data points suitable for the release envelope modulation function for a musical tone. The envelope modulation function for the attack phase of the tone production is obtained by computing a set of points as a fixed constant minus the data value for the corresponding decay point. The described envelope generator creates the envelope data points in the form of floating point binary numbers. The present invention can be advantageously incorporated into the musical tone envelope generator to provide an efficient and economical means for obtaining the attack phase envelope points by furnishing the complements of the generated decay values represented as binary floating point numbers.